Astera Labs

Founded in 2017 and headquartered in Santa Clara, CA, Astera Labs builds the 'connective tissue' inside AI infrastructure: its Aries PCIe/CXL Smart Retimers extend signal integrity across long PCIe 5/6 channels and cable runs; its Taurus Active Electrical Cables push 800G Ethernet between switches and NICs with full NVIDIA Spectrum-X interoperability; its Leo CXL Smart Memory Controllers enable CXL memory pooling (deployed on Microsoft Azure M-Series in 2025); and its Scorpio Smart Fabric Switch family — scaling from 32 to 320 lanes — provides open, memory-semantic scale-up interconnect for large GPU clusters. The company went public on NASDAQ in March 2024 (ticker: ALAB), raising roughly $713 million at a ~$5.5B implied valuation, and reported record full-year 2025 revenue with all four product families growing. Founders Jitendra Mohan, Sanjay Gajendra, and Casey Morrison were named EY World Entrepreneur Of The Year 2026.

As AI clusters scale to tens of thousands of accelerators, PCIe, CXL, and fabric bandwidth become the binding constraint — Astera Labs is one of the few pure-play fabless companies with a full-stack of shipping silicon specifically engineered for that bottleneck, across every major hyperscaler.

asteralabs.com Networking & Custom SiliconUSApublic · ALAB

At a glance

Total raised

$712.8M

last round ipo

Headcount

—

no public estimate on record

Headquarters

Santa Clara

USA

Founded

2017

9 years active

Status

Public

Ticker · ALAB

Latest valuation

$5.5B

IPO · 2024

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Funding history

Total raised

$712.8M

Rounds tracked

Latest stage

IPO

Latest valuation

$5.5B

Date	Stage	Amount	Valuation	Lead investors
Mar 20, 2024	IPO	$712.8M	$5.5B	—
Nov 17, 2022	Series D	$150M	$3.1B	Fidelity Management and Research
Sep 27, 2021	Series C	$50M	$950M	Fidelity Management and Research
Apr 22, 2020	Series B	—	—	Sutter Hill Ventures, Intel Capital
Mar 21, 2018	Series A	$16.5M	—	Intel Capital

Stock performance

How they make money

Hardware + recurring servicesPattern

Astera Labs is a fabless semiconductor company: it designs connectivity chips and sells them to original equipment manufacturers, original design manufacturers, and hyperscalers who integrate the silicon into AI servers, storage systems, and networking equipment. Revenue is almost entirely product-driven — fiscal 2024 product revenue was $393 million versus $3.2 million from technology licensing/services — and follows the standard fabless model of one-time per-unit chip sales at negotiated volume pricing. Customers are large cloud infrastructure buyers (Microsoft, Amazon, and similar hyperscalers), and contracts are typically multi-year platform design-wins with forecast-based purchase orders rather than spot transactions, providing some revenue visibility. Average selling prices reflect the company's positioning as a performance-differentiated merchant silicon vendor rather than a commodity supplier, and gross margins in the 60–65% range are consistent with a premium fabless business. The "recurring services" component is small today — primarily technology licensing from IP and COSMOS software that provides telemetry and management across the Aries, Leo, and Scorpio families — but represents a strategic attach that deepens customer relationships and could grow as the installed base expands. Pricing is not publicly disclosed at the SKU level, but Astera competes on total system cost (power, BOM, design-cycle savings) rather than on chip price alone, supporting premium unit economics. All manufacturing is outsourced to third-party foundries (TSMC is the primary production partner), consistent with the fabless model.

Generated by editorial-sourced · June 4, 2026Analytical summary · not investment advice

Founder backgrounds

Jitendra Mohan

Co-founder & CEO

Earned a B.Tech in Electrical Engineering from IIT Bombay and an M.S. in Electrical Engineering from Stanford University. Spent 16 years at National Semiconductor Corporation (1996–2012) in progressively senior engineering roles, finishing as Design Director for high-speed interface products. Moved to Texas Instruments following its 2011 acquisition of National Semiconductor, where he served as General Manager for TI's High Speed Interface Business and Clocking Business (2012–2017). Co-founded Astera Labs in November 2017, recognizing that PCIe signal-integrity would become the binding constraint in AI server racks; has served as CEO and board member since. Led the company through its March 2024 NASDAQ IPO (ticker: ALAB) and holds over 35 granted patents. Named EY World Entrepreneur Of The Year 2026 alongside his co-founders.

Sanjay Gajendra

Co-founder, President & COO

Holds a master's degree in Engineering Management from the University of Colorado at Boulder. Began his career as a Senior Software Engineer at Wipro Limited (1996–2000), then joined National Semiconductor Corporation where he rose from Principal Software Engineer to Product Manager over eleven years (2000–2011). Continued at Texas Instruments post-acquisition, serving as Director of Product Management and then Product Line General Manager for datacenter and server connectivity products (2012–2017). Co-founded Astera Labs in November 2017; also served as CFO and Treasurer from founding through July 2020, then as COO, and assumed the additional title of President in November 2023. Named EY World Entrepreneur Of The Year 2026.

Casey Morrison

Co-founder & Chief Product Officer

Holds an M.S. in Electrical Engineering from the University of Florida and gained early experience as an Electrical Engineering intern at Texas Instruments and Honeywell Aerospace. Joined Texas Instruments full-time, where he served in Systems and Applications Engineering roles within the Data Path Solutions product line, focusing on architectural definition, system simulation, and validation of high-speed interface products across PCIe, Ethernet, SAS/SATA, CPRI, and other serial standards; finished as Systems Engineering Manager and Head of Systems and Applications Engineering. Co-founded Astera Labs in 2017, leading the product organization and customer integration strategy for the company's full Intelligent Connectivity Platform. Named EY World Entrepreneur Of The Year 2026.

AI bull / bear

Bull case

Astera Labs occupies a structurally advantaged position as one of the few pure-play fabless companies with a full-stack of shipping silicon purpose-built for AI data-center connectivity: PCIe/CXL retimers (Aries), Ethernet active electrical cables (Taurus), CXL memory controllers (Leo), and fabric switches (Scorpio). This breadth across every major AI interconnect standard is difficult to replicate quickly, and deployment wins at scale — including the first public-cloud production CXL memory pooling on Microsoft Azure M-Series (2025) and a $2.5 billion Scorpio-X fabric opportunity tied to AWS cluster ramps in 2026–2029 — demonstrate the company is embedded in hyperscaler infrastructure roadmaps rather than sitting at the periphery. Revenue grew 242% in fiscal 2024 to $396 million and continued accelerating into 2025 (Q1 2025 up 144% YoY), with analysts forecasting a ~37% sales CAGR through 2027 as all four product families contribute. The founding team brings deep Texas Instruments and National Semiconductor pedigree in exactly these standards, was recognized as EY World Entrepreneur Of The Year 2026, and holds more than 35 patents providing durable IP defense. Astera's competitive moat compounds with each product-family win: retimer sockets pull through fabric-switch evaluation, CXL deployments create ongoing engagement with memory architects, and the proprietary COSMOS software that spans the platform creates switching friction. The merchant silicon market for scale-up switches alone is forecast to reach ~$20 billion by 2030, and Astera's open-architecture Scorpio positions it against closed proprietary fabrics (NVLink) in clusters where customers prize vendor diversity.

Bear case

The company is highly concentrated in a handful of hyperscale customers — Amazon/AWS, Microsoft, and a small number of other CSPs likely account for the overwhelming majority of revenue — meaning any single platform delay, internal custom-ASIC substitution, or procurement pause creates outsized revenue risk. Customer concentration also limits Astera's pricing leverage, and gross margins, while improving, remain under pressure from the cost structure of a pure-play fabless vendor with no services attach. At trading multiples that have reflected 20–50x forward revenue at various points since the IPO, the stock embeds an extremely high growth expectation; any single-quarter revenue miss or guidance cut could produce a 20–30% correction regardless of the underlying technology merits. Competitive pressure is real and intensifying: Broadcom and Marvell both have PCIe retimer and active-copper-cable products and the balance sheets to absorb pricing aggression; NVIDIA's NVLink dominates the highest-bandwidth scale-up tier and may reduce the addressable window for open-fabric alternatives; and the faster-than-expected transition to co-packaged optics (CPO) at the chip level would structurally shrink the retimer market before Scorpio fabric revenue is large enough to compensate. Execution risk on the Scorpio X-Series (320-lane) ramp — still targeting 2H 2026 production — is the single largest near-term variable, as any slip would push out the most significant growth vector by 12+ months.

Generated by editorial-sourced · June 4, 2026Refreshes quarterly · see disclosures

In the news

Astera Labs · last 30 days

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Leadership

Jitendra Mohan

Co-founder & CEO & CEO & Co-founder

—

Sanjay Gajendra

Co-founder, President & COO

—

Casey Morrison

Co-founder & Chief Product Officer & Chief Product Officer & Co-founder

—

Desmond Lynch

CFO (effective March 2, 2026; previously CFO of Rambus)

—

Products

Aries PCIe/CXL Smart Retimers & Smart Cable Modules
Signal-conditioning retimers that extend PCIe Gen 5 and Gen 6 channels across long traces, connectors, and cables inside AI servers and scale-out racks, including the industry's first purpose-built PCIe 6 gearbox bridging Gen 6 devices to Gen 5 infrastructure. The Smart Cable Module variant enables pluggable active copper interconnect at full PCIe/CXL compliance. Aries grew ~70% year-over-year in 2025 and is deployed at major hyperscalers.
Taurus Ethernet Active Electrical Cables (AEC)
800G per-link active electrical cables with integrated Ethernet PHY logic that extend switch-to-switch and switch-to-NIC reach up to 7 m, fully interoperable with NVIDIA Spectrum-X switching and ConnectX-8 NICs. Taurus provides a lower-power, lower-cost alternative to active optical cables for within-rack and top-of-rack AI network wiring.
Leo CXL Smart Memory Controllers
CXL 2.0/3.0 memory controllers that pool DDR5 DRAM modules as a shared, byte-addressable memory tier across hosts, reducing stranded memory capacity and lowering cost per GB in AI training and inference servers. Deployed on Microsoft Azure M-Series VMs in 2025, representing the first major public-cloud production deployment of CXL memory pooling.
Scorpio Smart Fabric Switch
Open, memory-semantic PCIe fabric switches spanning 32- to 320-lane configurations (P-Series and X-Series) that interconnect GPUs and accelerators within scale-up clusters with minimal latency. The Scorpio X-Series 320-lane switch is the industry's largest open fabric switch targeting the ~$20B merchant scale-up switch silicon market by 2030, with production ramp expected in 2H 2026.