Google Quantum AI's Willow chip demonstrated exponential logical-error suppression as surface-code distance grew (Dec 2024), and IBM Quantum's Heron r2/r3 processors are its primary vehicle for surface-code error correction on the path to fault tolerance by 2029. Surface codes require roughly 1,000 physical qubits per logical qubit, making scale hard.

IBM Quantum pivoted to quantum LDPC codes in 2024 as a path to dramatically lower physical-qubit overhead. Riverlane, which builds the error-correction 'decoder' layer, is hardware-agnostic and actively developing decoders optimized for qLDPC structures that work within the latency window of real hardware.

Alice & Bob and Nord Quantique are pursuing cat-qubit architectures that suppress one error type (bit flips) in hardware, reducing the overhead burden on software error correction. The bet is that hardware-level bias-preservation can reduce the physical-to-logical qubit ratio by an order of magnitude.

IBM Quantum (Heron r2/r3), Rigetti Computing, and Google Quantum AI are chasing 99.9%+ two-qubit gate fidelity on superconducting platforms. Rigetti's Cepheus-1 system targets 99.7% median two-qubit fidelity on its 108-qubit system in 2026.

IonQ and Quantinuum achieve the highest published two-qubit gate fidelities (>99.9%) using trapped ions, with IonQ publishing a complete fault-tolerant architectural blueprint in 2026. The challenge is clock speed — trapped-ion gates run in microseconds vs. nanoseconds for superconductors.

QuEra Computing, Pasqal, and Atom Computing use neutral atoms in optical tweezers, enabling reconfigurable qubit connectivity and competitive fidelity. QuEra and Atom Computing demonstrated 96 and 24 logical qubits respectively in 2025–2026 using neutral-atom hardware.

IBM Quantum presented cryo-CMOS ASICs for superconducting qubit flux control at APS 2026. Quantum Machines builds full-stack quantum control systems and has integrated cryo-compatible microwave amplification via a commercial agreement with Qblox, reducing room-temperature electronics dependencies.

Qblox and Quantum Machines both supply modular, dense control hardware targeting 1,000+ qubit systems without moving control electronics into the fridge. The tradeoff is I/O count and latency rather than thermal load.

PsiQuantum's all-photonic approach sidesteps cryogenic control at scale; Photonic Inc. is building silicon-spin qubits with photonic interconnects to distribute quantum processors across modules that each stay within cooling limits, avoiding the single-fridge wiring wall.

Riverlane is the leading independent specialist building hardware-accelerated decoders (the 'Decoder API') as a layer that sits between any qubit hardware and classical control. Q-CTRL approaches the problem from the firmware layer, combining machine-learning pulse optimization with software-defined error suppression.

Google Quantum AI's Willow results relied on minimum-weight perfect matching decoders that scale with code distance. Academic groups and startups are racing to find decoders that match the accuracy of MWPM at a fraction of the computational cost — required for any practical system running thousands of logical qubits.

IBM Quantum's cryo-CMOS work at APS 2026 targets moving parts of the decoding pipeline into the cold stage to eliminate round-trip latency. This is the furthest-out approach but potentially the only path for the deepest circuits.

Converting superconducting qubit states (microwave) to photons (optical) for long-distance transfer is pursued by academic groups at Caltech, MIT, and NIST, as well as companies like Photonic Inc., which is commercializing silicon-spin qubits with integrated photonic interconnects.

DARPA's HARQ program funded 19 teams in April 2026 across MOSAIC (software optimization across qubit types) and QSB (hardware interconnects). IonQ was publicly named as a HARQ participant, focusing on modular quantum networking using ion-trap systems linked by photonic interconnects.

Classiq offers a high-level synthesis layer that abstracts qubit-level compilation, targeting both NISQ and fault-tolerant targets. Agnostiq's Covalent orchestration framework manages hybrid classical-quantum workflows across cloud backends, helping developers avoid hand-optimizing circuits for each hardware target.

Q-CTRL's Boulder Opal applies machine-learning pulse shaping at the firmware level to reduce effective error rates before the software compiler even sees them. QC Ware specializes in algorithm-to-hardware co-design, working with financial and pharmaceutical customers to squeeze useful computation out of near-term hardware.

SandboxAQ and Multiverse Computing target specific verticals (life sciences, finance) where they can co-design both the algorithm and the compilation pipeline for a particular hardware type, sidestepping the general compilation problem by narrowing the scope.

Academic groups at Harvard, MIT, and Delft (QuTech) are the leading researchers. No FOBI roster company is yet commercializing stand-alone quantum memory, though IonQ's trapped-ion architecture inherently includes quantum memory as qubits can hold states for seconds, and its HARQ work includes quantum interconnect development.

Photonic Inc. is building silicon spin-photon interfaces that could serve as quantum memory nodes in a distributed network. Silicon carbide and diamond nitrogen-vacancy centers are the leading physical platforms in academic labs (MIT, TU Delft), with room-temperature operation as the long-term goal.