SiFive

SiFive licenses RISC-V processor IP and builds custom silicon solutions for AI, automotive, and data-center customers. Raised $500M+ including from Intel and Qualcomm; Intelligence X280 AI cores announced. RISC-V adoption accelerating in China.

SiFive is the leading commercial RISC-V IP provider, enabling open-architecture chips that challenge Arm and x86 incumbents.

sifive.com EDA & IPUSAprivate

At a glance

Total raised

$764.5M

last round series g

Headcount

—

no public estimate on record

Headquarters

San Mateo

USA

Founded

2015

11 years active

Status

Private

EDA & IP

Latest valuation

$3.6B

Series G · 2026

For subscribers

Subscribe to see the full profile

Including Funding rounds, Bull / Bear thesis, Stock + earnings, Roster changes, Patents, News, and Open roles.

Founding

50% off

/month

91 of 100 spots left

Full

$10

/month

Available once all 100 Founding Member spots are claimed.

Get full access

Already subscribed? Sign in →

Funding history

Total raised

$764.5M

Rounds tracked

Latest stage

Series G

Latest valuation

$3.6B

Date	Stage	Amount	Valuation	Lead investors
Apr 9, 2026	Series G	$400M	$3.6B	Atreides Management
Mar 1, 2022	Series F	$175M	$2.5B	Coatue Management
Aug 1, 2020	Series E	$60M	—	SK Hynix, Saudi Aramco
Jun 6, 2019	Series D	$65.4M	—	Sutter Hill Ventures, Spark Capital
Apr 2, 2018	Series C	$50.6M	—	Intel Capital
May 1, 2017	Series B	$8.5M	—	—
Sep 1, 2015	Series A	$5M	—	—

How they make money

Enterprise licensePattern

SiFive operates a semiconductor intellectual-property licensing model: customers pay upfront license fees for access to RISC-V processor core designs, plus ongoing royalties on chips that incorporate those cores. The company sells to fabless semiconductor firms, OEMs designing custom ASICs, and data-center operators building AI accelerators or automotive SoCs. Revenue is recognized at license signing for the upfront fee and ratably as chips ship for the royalty stream. The economics mirror ARM's model, where license fees cover R&D cost recovery and royalties provide long-tail margin as volume scales. Custom silicon services — designing bespoke chips for a specific customer — generate additional project-based revenue but carry higher delivery cost. What scales is the IP library: once a core is designed, licensing it to dozens of customers incurs near-zero marginal cost, which pushes gross margins into the typical semiconductor IP range of 70–90% at scale. SiFive subsidizes early-stage engagement and tooling to lock customers into its RISC-V ecosystem, betting on volume royalties down the line. No cost or revenue figures are public given the company is private.

Generated by deepseek-v4-flash · June 2, 2026Analytical summary · not investment advice

Founder backgrounds

Krste Asanović

Co-founder & Chief Architect

Holds a Ph.D. in computer science from UC Berkeley (1998). Joined MIT's faculty after his doctorate, receiving tenure in 2005, then returned to Berkeley in 2007 where he is now Professor Emeritus. Led the Berkeley RISC-V project, co-creating the RISC-V ISA in 2010 as an open, extensible instruction set architecture. Serves as Chief Architect at RISC-V International. Co-founded SiFive in 2015 with Yunsup Lee and Andrew Waterman to commercialize RISC-V processor IP, enabling semiconductor companies to license customizable RISC-V cores without royalties. Named ACM Fellow and IEEE Fellow.

Yunsup Lee

Co-founder & CTO

Earned his Ph.D. in computer science from UC Berkeley, where he co-designed the RISC-V ISA and co-built the first RISC-V microprocessors alongside Andrew Waterman under the supervision of Krste Asanović. His doctoral work also produced the Hwacha decoupled vector-fetch extension for RISC-V. Co-founded SiFive in 2015 to commercialize the open RISC-V ISA through silicon IP licensing, enabling custom processor designs without proprietary architecture fees. Serves as CTO, guiding the company's RISC-V core portfolio targeting AI, data center, and embedded applications.

Andrew Waterman

Co-founder & Chief Engineer

Earned his Ph.D. in computer science from UC Berkeley, where he co-designed the RISC-V ISA and co-built the first RISC-V microprocessors alongside Yunsup Lee and Krste Asanović starting in 2010. RISC-V emerged from Berkeley's 2010 effort to create a simple, clean-slate open ISA suitable for both research and commercial use. Co-founded SiFive in 2015 to turn that research into a commercial processor IP business. Serves as Chief Engineer, maintaining deep involvement in SiFive's RISC-V core architecture and contributing to RISC-V International specifications.

AI bull / bear

Bull case

SiFive sits at the fulcrum of the biggest architectural shift in silicon in decades. RISC-V adoption is accelerating in China, where geopolitical tensions are pushing domestic chip designers away from Arm and x86 toward open-standard alternatives. SiFive has raised over $500 million from Intel and Qualcomm, two of the most strategically important semiconductor companies on the planet that would rather pay for RISC-V progress than watch Arm collect tax on every data-center and mobile chip. The Intelligence X280 AI core positions SiFive to capture inference workloads at the edge and in the data center, exactly where AI processing is migrating off GPUs onto purpose-built accelerators. SiFive is not just another IP licensor; it is the only independent, large-scale RISC-V IP company with the engineering depth and customer relationships to challenge Arm. If even a fraction of the Chinese and Western RISC-V pipeline converts into production designs, SiFive's royalty stream grows from negligible to transformative.

Bear case

SiFive has not closed a publicly announced funding round in over two years, raising questions about its burn rate and path to profitability. The company has spent more than $500 million but lacks a marquee, high-volume customer design win that generates meaningful royalty revenue. China poses a double-edged sword: the same geopolitics that push RISC-V adoption also restrict SiFive's ability to license to Chinese companies under export controls, and Chinese RISC-V startups like Alibaba's T-Head offer competitive cores without U.S. exposure risk. Meanwhile, Arm continues to dominate mobile, cloud, and automotive with superior software ecosystems, developer toolchains, and binary compatibility guarantees that RISC-V cannot yet match. Intel's investment in SiFive was initially seen as a strategic bet, but Intel's own foundry struggles and layoffs suggest that support may waver. Without a blockbuster customer win in the next 12-18 months, SiFive risks becoming a cautionary tale of open-source hype over commercial traction.

Generated by deepseek-v4-flash · June 2, 2026Refreshes quarterly · see disclosures

In the news

SiFive · last 30 days

No articles ingested yet for SiFive. Once the hourly news pipeline is live, every article the classifier tags as mentioning this company appears here with its one-line AI summary and sentiment.

Watch

Leadership

Krste Asanović

Co-founder & Chief Architect

—

Yunsup Lee

Co-founder & CTO & Chief Technology Officer

—

Andrew Waterman

Co-founder & Chief Engineer

—

Patrick Little

Chairman, President & CEO

Products

SiFive Intelligence X280
SiFive's flagship AI/ML RISC-V processor, a multi-core-capable core with the RISC-V Vector extension plus SiFive Intelligence Extensions, optimized for vector and matrix compute from edge devices to the data center. Its Vector Coprocessor Interface Extension (VCIX) lets customers attach their own accelerators directly to the vector pipeline. The X280 is widely designed in, including as a control/host core in Google's data-center AI silicon.
Performance & Essential Core IP (P/E Series)
SiFive's licensable RISC-V CPU portfolio spanning the high-performance Performance (P) series out-of-order application cores and the area-efficient Essential (E) series for embedded and control tasks. These configurable cores let chipmakers build custom SoCs on the open RISC-V ISA instead of licensing Arm, and underpin SiFive's design wins across automotive, mobile, data-center, and aerospace/defense markets.
Data-Center RISC-V IP (NVLink Fusion)
SiFive's push into AI data-center silicon, including RISC-V IP designed to interoperate with Nvidia's NVLink Fusion so partners can build custom CPUs and accelerators that connect into Nvidia's rack-scale fabric. This positions SiFive's high-performance cores as host and companion processors in next-generation AI systems, extending RISC-V from the edge into large-scale AI infrastructure.

Most recent patents

57 patents on file, but none with both an extractable figure and an abstract on Google Patents yet.