Synopsys

Synopsys provides electronic design automation (EDA) software and IP that nearly every chip company uses to design semiconductors. Dominates logic synthesis and verification; AI-driven chip design tools (DSO.ai) gaining traction. Market cap ~$80B.

Synopsys is one half of the EDA duopoly (with Cadence) that controls the software layer enabling all chip design worldwide.

synopsys.com EDA & IPUSApublic · SNPS

At a glance

Total raised

Undisclosed

no public funding on record

Headcount

—

no public estimate on record

Headquarters

Sunnyvale

USA

Founded

1986

40 years active

Status

Public

Ticker · SNPS

Patents on file

272

USPTO grants

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Funding history

Total raised

—

Rounds tracked

Latest stage

IPO

Date	Stage	Amount	Valuation	Lead investors
Feb 26, 1992	IPO	—	—	—

Stock performance

How they make money

Enterprise licensePattern

Synopsys operates an enterprise license model: semiconductor companies pay recurring annual or multi-year license fees for access to its electronic design automation (EDA) tool suite and IP libraries. The company licenses software for logic synthesis, verification, simulation, and increasingly AI-driven design optimization (DSO.ai), with the largest customers taking enterprise-wide bundles that cover thousands of engineers. Revenue is recognized ratably over the license term, with maintenance and support typically included or sold as separate renewals. The IP segment adds a licensing stream where pre-verified chip building blocks (PHY, memory interface, processor cores) are licensed per project or on a royalty basis against the customer's chip shipments. The model's structural strength is high switching cost — once a fabless or integrated device manufacturer builds its design flow around Synopsys tooling, swapping vendors risks tape-out delays measured in months. Gross margins for enterprise EDA licenses are typical of mission-critical engineering software, with incremental license seats carrying near-zero marginal cost. R&D investment is heavy (the company spends significantly on tool development and IP qualification), but the installed base renews at high rates, giving the model predictable, long-duration revenue streams.

Generated by deepseek-v4-flash · June 2, 2026Analytical summary · not investment advice

Founder backgrounds

Aart de Geus

Co-founder & Executive Chair (former CEO)

Holds an M.S. in electrical engineering from EPFL (École Polytechnique Fédérale de Lausanne) and a Ph.D. from Southern Methodist University. Began his career at General Electric in 1982, developing foundational semiconductor design and verification tools. Co-founded Synopsys in 1986, initially commercializing logic synthesis — the software that automates creation of digital chip designs from high-level hardware description language — a category Synopsys pioneered and dominated. Served as CEO from 1994 through January 2024, building Synopsys into one of two leading EDA companies globally alongside Cadence. Received the IEEE Robert N. Noyce Medal in 2007 and the Semiconductor Industry Association Robert N. Noyce Award in 2024. Now serves as Executive Chair.

AI bull / bear

Bull case

Synopsys owns two unassailable monopolies: logic synthesis and verification. Every chip design — from Apple's A-series to NVIDIA's Blackwell — passes through Synopsys tools at some stage. That installed base generates recurring revenue with switching costs measured in years, not quarters. DSO.ai, their AI-driven design space optimization tool, already logged over 300 production tapeouts by late 2023, shortening design cycles that once took months into weeks. Customers pay a premium for that time savings. The broader tailwind is insatiable: chip complexity explodes under AI and advanced-node geometries, requiring ever-more-powerful EDA tools. Synopsys's IP business (USB, PCIe, DDR memory controllers) adds a high-margin revenue stream that locks customers deeper into the ecosystem. With an $80B market cap and pricing power that rivals enterprise software peers, Synopsys is effectively a tollbooth on the entire semiconductor industry.

Bear case

Synopsys faces its strongest threat in a generation. Cadence has closed the gap in synthesis and is winning share in verification with its Xcelium simulator. Meanwhile, open-source alternatives like Verilator and Chisel are gaining credibility for non-critical designs, slowly eroding the duopoly's lock on the entry-level talent pipeline. The bigger risk is AI. Synopsys's DSO.ai is impressive, but Google, NVIDIA, and even Cadence (with Cerebrus) are racing to build their own AI-driven EDA workflows. If chipmakers develop internal tools that bypass traditional EDA for key design stages, Synopsys's role shrinks from indispensable gatekeeper to just another vendor. An $80B valuation assumes perpetual margin expansion, but customer concentration is real — a handful of hyperscalers and foundries account for a disproportionate share of spending. Any shift toward in-house tooling by those giants would crack the duopoly's pricing power. The bull case assumes the status quo holds; the semiconductor industry's history suggests it rarely does.

Generated by deepseek-v4-flash · June 2, 2026Refreshes quarterly · see disclosures

In the news

Synopsys · last 30 days

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Leadership

Aart de Geus

Co-founder & Executive Chair (former CEO)

—

Sassine Ghazi

President & CEO

—

Shelagh Glaser

Chief Financial Officer

—

Products

Fusion Compiler & Design Compiler
Synopsys's core RTL-to-GDSII digital implementation flow. Design Compiler is the long-dominant logic-synthesis tool, while Fusion Compiler unifies synthesis and place-and-route in a single data model for faster timing closure on advanced nodes. Used by virtually every major chip team, this implementation franchise is the foundation of Synopsys's leadership in the EDA duopoly with Cadence.
DSO.ai (Design Space Optimization AI)
An AI-driven autonomous chip-design tool that uses reinforcement learning to search vast design spaces and optimize power, performance, and area with far less human iteration. As the first commercially deployed AI chip-design system at scale, DSO.ai (now part of the broader Synopsys.ai suite) has produced hundreds of production tapeouts and exemplifies the shift toward AI-assisted semiconductor design.
VCS Verification & Verdi Debug
Synopsys's functional-verification stack. VCS is a high-performance RTL simulator for verifying chip behavior before fabrication, paired with the Verdi debug system for tracing failures across large designs. Verification consumes the majority of chip-development effort, and this toolset, alongside emulation and formal tools, is central to Synopsys's verification business.
Synopsys IP Portfolio
One of the industry's largest catalogs of silicon-proven interface and foundation IP, including controllers and PHYs for PCIe, DDR/HBM, USB, Ethernet, and UCIe die-to-die links, plus embedded processors and security IP. Chipmakers license these pre-verified blocks to cut design risk and time-to-market, making IP a large, high-margin pillar of Synopsys's revenue.

Most recent patents

272 patents on file, but none with both an extractable figure and an abstract on Google Patents yet.