Synopsys (SNPS) is a publicly traded EDA & IP company founded in 1986 and based in Sunnyvale, USA.
| Date | Stage | Amount | Valuation | Lead investors |
|---|---|---|---|---|
| Feb 26, 1992 | IPO | — | — | — |
Synopsys reported Q3 FY2026 revenue of $2.477 billion, up 42% year-over-year, driven by broad-based strength across Design Automation and contributions from the Ansys acquisition. GAAP diluted EPS was $2.84, while adjusted EPS reached $3.91, exceeding guidance highs. Operating income rose to $357.5 million from $165.3 million year-over-year, though GAAP net income surged 125% to $545.8 million. The company raised full-year revenue guidance to $9.715 billion (midpoint) and adjusted EPS guidance to $15.07 (midpoint), citing double-digit EDA growth and AI-driven demand. Design IP, which had contracted in prior periods, returned to year-over-year growth. Full-year adjusted operating margin is expected near 41.5% at midpoint.
Full-year revenue $9.69–9.74B; non-GAAP EPS $15.04–15.10

Synopsys explains in an AI Infra Summit interview why agentic AI for chip design needs deterministic tools beyond the LLM itself.

Tom's Hardware runs an AI Chip Design Week series, including an interview with OpenAI hardware VP Richard Ho on the Jalapeño inference ASIC co-developed with Broadcom.

Weekly roundup: Synopsys agent portfolio and OpenAI deal, Lam Research CFET modeling, TSMC Texas evaluation, and South Korea chip exports up 262%.

Synopsys announces AgentEngineer portfolio of autonomous chip-design agents on its new Autopilot platform, targeting GA by end of 2026.
Synopsys's core RTL-to-GDSII digital implementation flow. Design Compiler is the long-dominant logic-synthesis tool, while Fusion Compiler unifies synthesis and place-and-route in a single data model for faster timing closure on advanced nodes. Used by virtually every major chip team, this implementation franchise is the foundation of Synopsys's leadership in the EDA duopoly with Cadence.
An AI-driven autonomous chip-design tool that uses reinforcement learning to search vast design spaces and optimize power, performance, and area with far less human iteration. As the first commercially deployed AI chip-design system at scale, DSO.ai (now part of the broader Synopsys.ai suite) has produced hundreds of production tapeouts and exemplifies the shift toward AI-assisted semiconductor design.
Synopsys's functional-verification stack. VCS is a high-performance RTL simulator for verifying chip behavior before fabrication, paired with the Verdi debug system for tracing failures across large designs. Verification consumes the majority of chip-development effort, and this toolset, alongside emulation and formal tools, is central to Synopsys's verification business.
One of the industry's largest catalogs of silicon-proven interface and foundation IP, including controllers and PHYs for PCIe, DDR/HBM, USB, Ethernet, and UCIe die-to-die links, plus embedded processors and security IP. Chipmakers license these pre-verified blocks to cut design risk and time-to-market, making IP a large, high-margin pillar of Synopsys's revenue.