TSMC

TSMC is the world's largest contract chipmaker, manufacturing over 90% of the world's most advanced chips including Nvidia and Apple silicon. Building Arizona fabs under CHIPS Act; 2nm mass production targeted for 2025. Geopolitical risk remains central concern.

TSMC's monopoly on leading-edge logic nodes (3nm, 5nm) makes it the single most critical bottleneck in AI hardware supply.

tsmc.com Foundries

Taiwanpublic · TSM

At a glance

Total raised

$595M

last round ipo

Headcount

—

no public estimate on record

Headquarters

Hsinchu

Taiwan

Founded

1987

39 years active

Status

Public

Ticker · TSM

Patents on file

USPTO grants

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Funding history

Total raised

$595M

Rounds tracked

Latest stage

IPO

Date	Stage	Amount	Valuation	Lead investors
Oct 8, 1997	IPO	$595M	—	—

Stock performance

How they make money

Other (specify in prose)Pattern

TSMC operates a pure-play semiconductor foundry model: it manufactures chips designed by other companies and charges per wafer, with pricing tiered by process node (maturity), yield rate, and volume. Customers such as Nvidia, Apple, AMD, and Qualcomm bring their own chip designs, and TSMC fabricates those designs on its advanced logic nodes (3nm, 5nm, and soon 2nm). Revenue is recognized upon delivery of completed wafers to the customer — a straightforward manufacturing-services transaction per wafer lot, though customers typically commit to multi-year capacity reservations that provide revenue visibility. The economics are driven by capital intensity and process-technology leadership. TSMC invests tens of billions of dollars upfront in fabrication plants (fabs) and R&D to stay ahead on node shrinks. Once a fab is qualified and running at high yield, marginal cost per wafer drops sharply, creating significant operating leverage at scale. Leading-edge nodes command a premium over trailing-edge nodes, and TSMC's near-monopoly on sub-7nm manufacturing gives it substantial pricing power. The model is structurally similar to a high-end contract manufacturer with massive upfront capex and volume-based unit economics.

Generated by deepseek-v4-flash · June 2, 2026Analytical summary · not investment advice

Founder backgrounds

Morris Chang

Founder (former Chairman & CEO, retired)

Earned a B.S. and M.S. from MIT and a Ph.D. in electrical engineering from Stanford in 1964. Joined Sylvania Semiconductor in 1955, then Texas Instruments in 1958, where over 25 years he rose to Group VP overseeing global semiconductor operations and became known for his expertise in manufacturing yield improvement. Left TI in 1984 to serve briefly as President and COO of General Instrument before the Taiwan government recruited him to lead its semiconductor development initiative. Founded TSMC in 1987, inventing the dedicated foundry model — fabricating chips exclusively for fabless designers rather than competing with customers — a structure that became the foundation of the modern semiconductor industry. Led TSMC through its growth into the world's dominant contract chipmaker, serving as CEO and Chairman until his 2018 retirement.

AI bull / bear

Bull case

AI is remaking TSMC into a structurally different company. The firm already owns over 90% of leading-edge logic, and AI-related revenue is on track to hit one-third of total business. That is not cyclical demand — hyperscalers are building multi-year infrastructure cycles around NVIDIA and AMD silicon that only TSMC can fab at scale. The upcoming 2nm node (2025) extends the moat. No competitor — Samsung or Intel — has matched TSMC's yield consistency at 3nm or 5nm. The Arizona fabs, backed by CHIPS Act funding, gradually de-risk the Taiwan concentration argument. And when a customer like AMD has to re-engineer an entire processor because TSMC changed a bonding process, it proves the switching costs are immense. TSMC dictates terms because it owns the physics bottleneck in AI hardware.

Bear case

TSMC's monopoly is a single-point-of-failure that markets have already begun pricing. The Taiwan strait risk is unhedgeable — no Arizona fab cluster can replace the Giga-fabs in Hsinchu and Tainan within a decade. Even CHIPS Act subsidies cannot replicate TSMC's ecosystem density of suppliers, chemicals, and talent. Meanwhile, Intel's foundry push and Huawei's alternative transistor proposals signal that the biggest buyers want a second source. AMD's re-engineering headache with TSMC's bonding process shows what happens when a fab unilaterally changes a node — customers will fund alternatives. If geopolitical tensions escalate, TSMC could face export controls that sever it from its own customers. The monopoly that powers the bull case is also the fragility that could break it.

Generated by deepseek-v4-flash · June 2, 2026Refreshes quarterly · see disclosures

In the news

Watch

Leadership

Morris Chang

Founder (former Chairman & CEO, retired)

—

C.C. Wei

Chairman & CEO

—

Wendell Huang

SVP & Chief Financial Officer

—

Products

N2 (2nm) Process Technology
TSMC's 2nm-class node and its first to adopt gate-all-around nanosheet transistors, replacing FinFET to deliver higher performance and lower power at the leading edge. N2 entered high-volume manufacturing in late 2025 with good yield, and the N2P/N2U variants extend it with design-technology co-optimization. As the most advanced logic process available to merchant customers, N2 is where the next generation of AI accelerators, CPUs, and flagship mobile SoCs are built.
CoWoS Advanced Packaging
Chip-on-Wafer-on-Substrate, TSMC's 2.5D advanced-packaging platform that integrates large logic dies with stacks of HBM on a silicon interposer. CoWoS is the indispensable packaging behind virtually every high-end AI accelerator, including Nvidia's GPUs, and its capacity is a primary industry bottleneck. TSMC is scaling to 5.5-reticle interposers today with far larger versions (integrating ~10 compute dies and 20 HBM stacks) on the roadmap.
A16 / A14 Angstrom-Era Nodes
TSMC's sub-2nm roadmap. A16 pairs nanosheet transistors with Super Power Rail backside power delivery for dense, high-performance HPC designs; A14 introduces a second-generation nanosheet structure targeting another full-node gain (10-15% faster or 25-30% lower power, ~20% denser) with volume production planned for 2028. These nodes extend TSMC's leadership at the physical limits of transistor scaling for future AI and computing silicon.

Most recent patents

94 patents on file, but none with both an extractable figure and an abstract on Google Patents yet.

TSMC

At a glance

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Funding history

Stock performance

How they make money

Founder backgrounds

Morris Chang

AI bull / bear

In the news

AMD ‘had to re-engineer’ the Ryzen 7 5800X3D for a re-release — 10th Anniversary Edition chip had ‘a whole body of engineering work’ put into it

TSMC Defends Transistor Scaling Amid Huawei’s ‘Her’s Law’ Proposal

Watch

Leadership

Products

N2 (2nm) Process Technology

CoWoS Advanced Packaging

A16 / A14 Angstrom-Era Nodes

Most recent patents

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