TSMC (TSM) is a publicly traded Foundries company founded in 1987 and based in Hsinchu, Taiwan.
| Date | Stage | Amount | Valuation | Lead investors |
|---|---|---|---|---|
| Oct 8, 1997 | IPO | $595M | — | — |

Three contract workers die and a fourth is in intensive care after a steel-hoisting fall at TSMC's 2nm Fab 22 site in Kaohsiung.

TSMC's supply bottleneck raises questions about AI infrastructure spending and may open orders for Samsung and Intel.

Intel and TSMC now share a research floor at Applied Materials' EPIC Center in Santa Clara.

TSMC's 2026 OIP Ecosystem Forum frames AI as driving chip progress across logic, memory, packaging, interconnects, and power delivery.

Bernstein names TSMC, Samsung, and MediaTek as top semiconductor picks on sustained AI compute demand.

GlobalFoundries signs a five-year, $2B deal to produce silicon interposers for TSMC's CoWoS packaging at its Malta, NY fab.
TSMC's 2nm-class node and its first to adopt gate-all-around nanosheet transistors, replacing FinFET to deliver higher performance and lower power at the leading edge. N2 entered high-volume manufacturing in late 2025 with good yield, and the N2P/N2U variants extend it with design-technology co-optimization. As the most advanced logic process available to merchant customers, N2 is where the next generation of AI accelerators, CPUs, and flagship mobile SoCs are built.
Chip-on-Wafer-on-Substrate, TSMC's 2.5D advanced-packaging platform that integrates large logic dies with stacks of HBM on a silicon interposer. CoWoS is the indispensable packaging behind virtually every high-end AI accelerator, including Nvidia's GPUs, and its capacity is a primary industry bottleneck. TSMC is scaling to 5.5-reticle interposers today with far larger versions (integrating ~10 compute dies and 20 HBM stacks) on the roadmap.
TSMC's sub-2nm roadmap. A16 pairs nanosheet transistors with Super Power Rail backside power delivery for dense, high-performance HPC designs; A14 introduces a second-generation nanosheet structure targeting another full-node gain (10-15% faster or 25-30% lower power, ~20% denser) with volume production planned for 2028. These nodes extend TSMC's leadership at the physical limits of transistor scaling for future AI and computing silicon.